MRAM Basics
The basic MRAM cell is the so-called Magnetic Tunnel Junction (MTJ) which consists of two magnetic layers sandwiching a thin (sub-nm) insulating layer (see Fig. 1). The magnetization of one of the layers, acting as a reference layer, is fixed and kept rigid in one given direction. The other layer, acting as the storage layer, can be switched under an applied magnetic field from parallel to antiparallel to the reference layer, therein inducing a change in the cell resistance. The corresponding logic state ("0" or "1") of the memory is hence defined by its resistance state (low or high), monitored by a small read current.
A fully functional MRAM memory is based on a 2D array of individual cells, which can be addressed individually. In traditional architectures, each memory cell combines a CMOS selection transistor with a magnetic tunnel junction and three line levels, two of which are positioned in a cross point architecture (see figure 2). This technology has been used efficiently in the first generation of MRAM devices, developed so far with feature sizes greater than 0.13-0.18 µm.
Going further down the roadmap will require new architectures. CROCUS and its partner research centres SPINTEC and LETI have developed within the IST European program “NEXT” a unique technology protected by an broad IP portfolio. The CROCUS MRAM technology not only allows full scalability to technology nodes at 90nm and beyond, but also exhibits high speed, error-free addressing, reduced power consumption and radiation/magnetic field hardness.
